1. Field of the Invention
The present invention relates to a multiple reaction chamber system and a method of processing a wafer using the same, and more particularly, to a multiple reaction chamber system having an individual wafer recognition system, and a method of processing a wafer using the same.
2. Description of the Related Art
Because modem, highly integrated semiconductor devices are complicated to manufacture, manufacturing productivity can be increased by converting a single reaction chamber system into a multiple reaction chamber system.
As shown in FIG. 1, a conventional multiple reaction chamber system 26 includes a transfer chamber 10 and a plurality of other chambers connected to the transfer chamber 10. More specifically, first and second load lock chambers 12 and 14, and an align chamber 16 having a wafer aligner 16a for aligning wafers, are connected to the transfer chamber 10. First and second reaction chambers 18 and 20 are also connected to the transfer chamber 10. Each chamber is closed to prevent wafers from being exposed to air.
In FIG. 1, solid line arrows A, dashed line arrows B and dotted line arrows C indicate the various paths for moving a wafer among the chambers.
A wafer loaded in either the first or second load lock chamber 12 or 14, for example, the first load lock chamber 12, is transferred to the align chamber 16 along one of the solid line paths A. After the wafer is aligned in the align chamber 16, the wafer is transferred to either the first or second reaction chamber 18 or 20, for example, the first reaction chamber 18, along one of the other solid line paths A. The reaction chamber 18 or 20, for example, the first reaction chamber 18, processes the wafer. Then, the wafer is transferred to the first load lock chamber 12 via the transfer chamber 10 along one of the dashed line paths B, or to the second load lock chamber 14 via the transfer chamber 10 along one of the dotted line paths C. The other wafers loaded in the first and second load lock chambers 12 and 14 are also handled through the same alternative paths as the first selected wafer.
When a wafer is not properly processed due to a malfunction of the first reaction chamber 18, the second reaction chamber 20 should be used instead of the first reaction chamber 18. However, when the conventional multiple reaction chamber system is used the previous paths are simply repeated. Thus, some wafers will continue to be processed in the malfunctioning reaction chamber. Accordingly, the wafer processing process continues until inferior wafers are detected among the processed wafers. Furthermore, even when inferior wafers are detected, it is not known which reaction chambers they were processed in. Thus, a lot of time is required to solve the problem, so that productivity of the semiconductor device manufacturing facility is lowered.